Semiconductor memory circuit and control method for reading data

ABSTRACT

A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

CROSS REFERENCE TO RELATED APPLICATION

This application is a U.S. divisional application filed under 37 USC 1.53 claiming priority benefit of U.S. Ser. No. 12/685,854 filed in the United States on Jan. 12, 2010, which claims earlier priority benefit to Japanese Patent Application No. 2009-014755 filed on Jan. 26, 2009, the disclosures of which are incorporated herein by reference.

FIELD

The embodiment discussed herein are related to semiconductor memory circuit and control method for reading data.

BACKGROUND

Hitherto, in order to store various data in a semiconductor integrated circuit, a semiconductor memory circuit such as an SRAM and a DRAM have been used.

-   [Patent Document 1] Japanese Laid-open Patent Publication No.     2006-331568 -   [Non patent Document 1] Kevin Zhang, Ken Hose, Vivek De, and Borys     Senyk “The Scaling of Data Sensing Schemes for High Speed Cache     Design in Sub-0.18 μm Technologies” Symposium on VLS1 Circuits     Digest of Technical Papers, PP 226-227, 2000. -   [Non patent Document 2] J. Davis, D. Plass, P. Bunce, Y. Chan, A.     Pelella, R. Joshi, A. Chen, W. Huott, T. Knips, P. Patel, K. Lo,     and E. Fluhr “A 5.6 GHz 64 kB Dual-Read Data Cache for the POWER6     Processor” IEEE International Solid-State Circuits Conference, 2006.

The semiconductor memory circuit has adopted a dynamic circuit in which a single p-type MOS transistor connects to a single bit line. The adoption of the dynamic circuit may reduce the load capacity of the bit line more than a static circuit because only one transistor connects to the bit line and thus may increase the operation speed. Also, since the dynamic circuit may be configured by a lower number of transistors, which may reduce the circuit area.

The semiconductor memory circuit in the past having a column selection circuit in the local bit line as illustrated in FIG. 6A has a lower discharge speed of the local bit line, resulting in a decrease in reading speed.

As illustrated in FIGS. 6A and 6B and FIG. 7, the addition of a local read circuit configured by two or more transistors such as an inverter and a NAND to the end of the local bit line may reduce the discharge speed of the local bit line. As a result, the reading speed of the semiconductor memory circuit may decrease.

As illustrated in FIG. 7 and FIG. 8, the column selection in global reading instead of column selection in local reading using a local read circuit may possibly include charging/discharging in the global bit line for all columns, which may increase the power consumption.

In FIG. 8, the reading speed is increased by a pre-discharge dynamic circuit having the end of the local bit line connecting to one p-type transistor. in FIG. 8). However, since, as described above, the column selection is not performed in the local region, the power consumption disadvantageously increases. For example, the addition of a column selection circuit to the circuit illustrated in FIG. 8 may also necessarily increase the number of transistors. Both of a pre-discharge signal and column selection signal may be required to input to the local region, which may also require the wiring area there for. For these reasons, building the column selection circuit into the circuit illustrated in FIG. 8 increases the size of circuit. FIGS. 6A and 6B to FIG. 8 are diagrams of circuit configurations in the past.

SUMMARY

According to an aspect of embodiments, a semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a circuit configuration of a semiconductor memory circuit according to a first embodiment;

FIG. 2 is a diagram for explaining the semiconductor memory circuit according to the first embodiment;

FIG. 3 is a diagram for explaining the semiconductor memory circuit according to the first embodiment;

FIG. 4 is a diagram illustrating signal waveforms according to the first embodiment;

FIG. 5 is a diagram illustrating a circuit configuration of a semiconductor memory circuit according to a second embodiment;

FIGS. 6A and 6B are diagrams of circuit configurations in the past;

FIG. 7 is a diagram of circuit configuration in the past; and

FIG. 8 is a diagram of circuit configuration in the past.

DESCRIPTION OF EMBODIMENTS

A semiconductor memory circuit and a control method for reading data according to an embodiment will be described in detail below.

A semiconductor memory circuit according to a first embodiment includes a read circuit, which is a dynamic circuit having a bit line connecting to a single p-type transistor. There are two essential features of the semiconductor memory circuit according to the first embodiment. The first feature is that the read circuit includes a p-type transistor that is located in series between another p-type transistor connecting to the bit line and a power supply and is connected to a read-column selection line. The second feature is that the read circuit further includes an n-type transistor connecting to a read-column selection line. The semiconductor memory circuit according to the first embodiment will be described more specifically below.

FIG. 1 is a diagram illustrating a circuit configuration of the semiconductor memory circuit according to the first embodiment. FIG. 2 is a diagram for explaining the semiconductor memory circuit according to the first embodiment. This semiconductor memory circuit has a circuit configuration as illustrated in FIG. 1. With reference to FIG. 2, this semiconductor memory circuit will be described below.

As illustrated in FIG. 2, the semiconductor memory circuit according to the first embodiment includes a plurality of bit cells 10 that connect to local bit lines 70 and word lines 20 and hold information.

The semiconductor memory circuit further includes a pre-charge circuit 30 that connects to a local bit line pre-charge line 40 and the local bit lines 70 and pre-charges the local bit lines 70 on the basis of the input from the local bit line pre-charge line 40.

The semiconductor memory circuit further includes a read circuit 200 as will be described below. That is, the read circuit 200 has a p-type transistor P2 having a source terminal connected to a power supply and a gate terminal connected to a read-column selection line 90.

The read circuit 200 further has a p-type transistor P1 that has a source terminal connected to the drain terminal of the p-type transistor P2, a gate terminal connected to one of the local bit lines, and a drain terminal connected to a sense out line 80 and, on the basis of the input from the read-column selection line 90 and the potential level of the local bit line 70, charges the sense out line 80. The read circuit 200 further has an n-type transistor N1 that has a drain terminal connected to the sense out line 80, a gate terminal connected to the read-column selection line 90 and a source terminal grounded and pre-discharges the global-bit-line driver control line on the basis of a column selection signal. The read circuit 200 further has an n-type transistor N2 that has a drain terminal connected to a global bit line, a gate terminal connected to the sense out line 80 and a source terminal grounded.

In the read circuit 200, on the basis of the input from the charged sense out line 80, the n-type transistor N2 is brought into conduction. Thus, the column having the corresponding local bit line is selected, and the information held in the bit cell 10 having the word line 20 driven among the plurality of bit cells 10 is read from a global bit line 110.

The semiconductor memory circuit according to the first embodiment further includes, as illustrated in FIG. 2, a write circuit 300 connecting to a write-column-selection line 310 and a write data input line 320. On the basis of the input from the write-column-selection line 310, the column having the corresponding local bit line is selected, and the data is written from the write data input line 320 to the bit cell 10 having the word line 20 driven among the plurality of bit cells 10.

According to an embodiment, the bit cell 10 may also be referred to as “bit cell”; the word line 20 may also be referred to as “word line”; the pre-charge circuit 30 may also be referred to as “first pre-charge control circuit”; the local bit line pre-charge line 40 may also be referred to as “first pre-charge control line”; the local bit line 70 may also be referred to as “first bit line” or “second bit line”; the sense out line 80 may also be referred to as “global-bit-line driver control line”; the read-column selection line 90 may also be referred to as “column selection line”; the global bit line pre-charge line 100 may also be referred to as “third pre-charge control line,” and the global bit line 110 may also be referred to as “third bit line.”

According to an embodiment, the p-type transistor P1 may also be referred to as “second transistor”; the p-type transistor P2 may also be referred to as “first transistor”; the n-type transistor N1 may also be referred to as “third transistor,” and the n-type transistor N2 may also be referred to as “fourth transistor.”

According to an embodiment, the write circuit 300 may also be referred to as “writing control circuit”; the write-column-selection line 310 may also be referred to as “write-column-selection line,” and the write data input line 320 may also be referred to as “write data input line.”

With reference to FIG. 3, a bit-cell selecting method in the read circuit 200 will be described below. FIG. 3 is a diagram for explaining the semiconductor memory circuit according to the first embodiment. FIG. 1 and FIG. 2 illustrate only a single line of the bit cells 10, for simplification. Generally, as illustrated in FIG. 3, the plurality of bit cells is arranged in a semiconductor memory circuit.

For example, in response to a read request from a host, not depicted, the bit cell 10 holding the data corresponding to the read request in the read circuit 200 is selected. More specifically, as illustrated in FIG. 3, the word line 20 is driven, and the row connecting to the bit cell 10 holding the data corresponding to the read request is selected thereby. Then, on the basis of the input from the read-column selection line 90, the column connecting to the bit cell holding the data corresponding to the read request is selected.

Next, with reference to FIG. 4, a reading operation routine in the read circuit 200 will be described. FIG. 4 is a diagram illustrating signal waveforms according to the first embodiment. The illustrated dashed arrow indicates signals that trigger the switching between “Hi” and “Lo” of the signals. In response to a read request and then on the basis of the input from the local bit line pre-charge line, the local bit line 70 is pre-charged. in FIG. 4). Next, on the basis of the input from the global bit line pre-charge line 100, the global bit line 110 is pre-charged. in FIG. 4).

As illustrated in FIG. 4, during the pre-charge on the local bit line 70 and global bit line 110, the input from the read-column selection line 90 has “Hi”. in FIG. 4). Thus, the n-type transistor N1 connected to the read-column selection line 90 is turned on, and the sense out line 80 is pre-discharged. As a result, the sense out line 80 is “Lo”. in FIG. 4).

Then, the word line 20 is “Hi”. in FIG. 4). When the input from the read-column selection line 90 is “Lo” in FIG. 4), the n-type transistor N1 is turned off. Since the input from the read-column selection line 90 has been changed to have “Lo”, the corresponding column has already been selected. On the other hand, when the input from the read-column selection line 90 is “Lo” in FIG. 4), the p-type transistor P2 is turned on. Conversely, when the word line 20 is “Hi”, the local bit line 70 is discharged. in FIG. 4). Thus, the p-type transistor P1 is turned on. When both of the p-type transistors P1 and P2 are turned on, charges are thus loaded from the power supply, and the sense out line 80 is charged. in FIG. 4).

The sense out line 80 having “Hi” turns on the n-type transistor N2. Thus, the global bit line 110 is discharged to “Lo”. After the global bit line 110 is discharged, “Lo” is output to the I/O circuit 400 as the reading result from the bit cell 10.

The reading operation in the read circuit 200 will be organized conceptually.: The entire row driven by a word line is read.: In the row, the column required by a read-column selection signal is only selected.: As a result, the sense out is charged.: The sense out charged in turns on the n-type transistor N2, and, as a result, the data in the memory/holding circuit selected by the word line and read-column selection signal is read.

As described above, since the semiconductor memory circuit according to the first embodiment includes the read circuit having a dynamic configuration connecting a bit line to the p-type transistor P1, the speed of discharging from the local bit line 70 may be increased. As a result, the reading speed by the read circuit 200 may be increased.

A semiconductor memory circuit in the past has shorter local bit lines as a measure against the variations among the performance for manufacturing transistors. However, the increase in number of divisions of bit lines increases the size of the layout in the direction of the bit lines. Thus, the amount of amount of charges charge to be loaded or unloaded to or from a global bit line increases. As a result, the power consumption increases. On the other hand, the semiconductor memory circuit according to the first embodiment includes the read circuit internally having the p-type transistor P2 connected in series to between a p-type transistor P1 connected to the local bit line 70 and the power supply and connecting to the read-column selection signal. Since the p-type transistor P2 may implement the column selection of a bit cell, the number of global bit line to be charged or discharged may be reduced. As a result, the power consumption may be reduced.

Within the read circuit 200, the n-type transistor N1 for pre-discharging the sense out line 80 is connected to a read-column selection signal. Thus, one signal line may be required for column selection and pre-discharging the sense out line 80. Thus, the size of the circuit may be reduced.

A semiconductor memory circuit and a control method for writing/reading data according to another embodiment will be described below.

[1] Application Example of Semiconductor Memory Circuit According to First Embodiment

For example, as illustrated in FIG. 5, the semiconductor memory circuit according to the first embodiment is applicable to a multiport semiconductor memory circuit. FIG. 5 is a diagram illustrating a configuration of a semiconductor memory circuit according to the second embodiment.

[2] Circuit Configuration and Others

The components of the semiconductor memory circuit illustrated in FIG. 1 are not always physically required to be arranged as in the illustrated configuration. In other words, the concrete forms of the distribution and integration of the components of the semiconductor memory circuit illustrated in FIG. 1 are not limited to the illustrated one, but all or a part of the components may be functionally or physically distributed and/or integrated in arbitrary units in accordance with the loads and/or the usages, within the range required for achieving the object of the embodiment.

[3] Control Method for Reading Data

The semiconductor memory circuit according to the first embodiment may implement the control method for reading data as follows:

There may be provided a control method for reading data in the semiconductor memory circuit, the method including a reading control step of performing reading control including, on the basis of the input from the pre-charged sense out line 80, bringing the n-type transistor N2 into conduction, selecting the column having the corresponding local bit line, and outputting the information held in the bit cell 10 having the word line 20 driven among the plurality of bit cells 10 to the global bit line 110.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a depicting of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A semiconductor memory device comprising: a plurality of memory circuits that connect to a first bit line, a second bit line, and a word line and that hold information; a pre-charge control circuit that connects to a first pre-charge control line, the first bit line, and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line; and a first read control circuit having a first transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; a second transistor that has a source terminal connected to a drain terminal of the first transistor, a gate terminal connected to the first bit line, and a drain terminal connected to a first global-bit-line driver control line and that charges the first global-bit-line driver control line on the basis of the input from the read-column selection line and the potential level of the first bit line; a third transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the read-column selection line, and a source terminal grounded; and a fourth transistor that has a drain terminal connected to a third bit line, a gate terminal connected to the first global-bit-line driver control line, and a source terminal grounded, wherein the column having the first bit line and the second bit line is thus selected on the basis of the input from the pre-charged first global-bit-line driver control line, the fourth transistor is brought into conduction, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the third bit line; and a second read control circuit having a fifth transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; and a sixth transistor that has a source terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to the second bit line, and a drain terminal connected to a second global-bit-line driver control line and, that charges the second global-bit-line driver control line on the basis of the input from the second read-column selection line and the potential level of the second bit line; a seventh transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the second read-column selection line, and a source terminal grounded and that pre-discharges the global-bit-line driver control line on the basis of column selection signal; and an eighth transistor that has a drain terminal connected to a fourth bit line, a gate terminal connected to the second global-bit-line driver control line, and a source terminal grounded, wherein the eighth transistor is brought into conduction on the basis of the input from the pre-charged second global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the fourth bit line.
 2. A control method for reading data in a semiconductor memory device, the semiconductor memory device having: a plurality of memory circuits that connect to a first bit line, a second bit line, and a word line and that hold information; a pre-charge control circuit that connects to a first pre-charge control line, the first bit line, and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line; and a first read control circuit having a first transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; a second transistor that has a source terminal connected to a drain terminal of the first transistor, a gate terminal connected to the first bit line, and a drain terminal connected to a first global-bit-line driver control line and that charges the first global-bit-line driver control line on the basis of the input from the read-column selection line and the potential level of the first bit line; a third transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the read-column selection line, and a source terminal grounded; and a fourth transistor that has a drain terminal connected to a third bit line, a gate terminal connected to the first global-bit-line driver control line, and a source terminal grounded, wherein the fourth transistor is brought into conduction on the basis of the input from the charged first global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in a memory circuit connecting to the driven word line among the plurality of memory circuits is output to the third bit line; and a second read control circuit having a fifth transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; and a sixth transistor that has a source terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to the second bit line, and a drain terminal connected to a second global-bit-line driver control line and, on the basis of the input from the second read-column selection line and the potential level of the second bit line, that charges the second global-bit-line driver control line; a seventh transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the second read-column selection line, and a source terminal grounded; and an eighth transistor that has a drain terminal connected to a fourth bit line, a gate terminal connected to the second global-bit-line driver control line, and a source terminal grounded, wherein the eighth transistor is brought into conduction on the basis of the input from the charged second global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the fourth bit line, the control method for reading data comprising: selecting the column having the first bit line and the second bit line by bringing the fourth transistor into conduction on the basis of the input from the charged first global-bit-line driver control line; reading the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits from the third bit line; selecting the column having the first bit line and the second bit line by bringing the eighth transistor into conduction on the basis of the input from the charged second global-bit-line driver control line; and reading the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits to the fourth bit line. 